1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to a transistor incorporating a channel-shaped gate dielectric layer, and to a method of making the same.
2. Description of the Related Art
Scaling of field effect transistor devices has historically been, and continues to be a fundamental goal in the semiconductor fabrication industry. The continual drive toward higher circuit density has been fueled by demands from ordinary consumers, industry, government and the military for ever increasing speed, capability and miniaturization of electronic products, as well as the desire of semiconductor manufacturer to reduce manufacturing costs. Scaling efforts have thus far been highly successful. Three micron processing, considered state of the art a little more than a decade ago, has given way to sub-micron processing.
As in many aspects of semiconductor processing, current scaling efforts involve a set of trade-offs between higher packing density and better performance, and short channel effects. As process technology scaled below about 2.0 .mu.m, a series of design difficulties arose stemming from the semiconductor physics associated with short-channel devices. Hot carrier effects and subthreshold leakage currents become much more problematic in short channel devices, such as modern field effect transistors in sub-2.0 .mu.m processing. If not compensated for through processing techniques or other means, such effects can either reduce device performance or lead to device failure or both.
One method commonly used to alleviate short-channel effects in field effect transistors is the incorporation of lightly-doped drain ("LDD") structures. The purpose of LDD structures is to absorb some of the gate-to-substrate potential into the drain of the transistor. As with many aspects of semiconductor processing, there are tradeoffs associated with the incorporation of LDD structures. LDD structures will render PMOS devices more resistance to hot carrier injection, but will also generally reduce the drive current due to a rise in the series resistance of the drain region. In addition, the formation of LDD increases fabrication complexity. At least two, and more often four separate masking steps are required for CMOS circuits. Aside from increased processing complexity, LDD structures represent a constraint on the packing density of transistors. Conventional LDD and source/drain structures extend laterally to either side of a gate electrode. Accordingly, substrate area must be set aside to accommodate for these laterally extending structures. This set aside of chip area must always be taken into account even if improvements in lithographic patterning reduce the minimum lateral feature size of devices on the substrate.
Another technique to combat short channel effects has involved the scaling of gate dielectrics. To compensate for the potentially lower drive currents for a given short channel device, conventional silicon dioxide gate oxide layers are made as thin as possible to maximize drive current. However, the scaling of silicon dioxide gate dielectric layers has introduced another set of problems. To begin with, very thin silicon dioxide layers have been historically difficult to fabricate with a consistent thickness across a given wafer, from wafer to wafer and from lot to lot. In addition, as the thickness of silicon dioxide is scaled downward, the potential for reliability problems associated with dielectric breakdown and hot and cold carrier injection degradation increases. Hot and cold carrier degradation can significantly reduce device performance, while dielectric breakdown can lead to complete device failure.
One potential cause of carrier injection and potential dielectric breakdown is thought to occur as a result of interface traps near the Si--SiO.sub.2 interface. Interface traps are the apparent result of dangling silicon bonds at the Si--SiO.sub.2 interface. Dangling Si bonds represent sites where hot carrier injection, Fowler-Nordheim tunneling and direct tunneling can occur. Although tunneling is thought to arise as a natural consequence of the quantum mechanical nature of electrons positioned near a very thin oxide layer, dangling Si bonds appear to exacerbate the problem. Independent of the exact physical cause of carrier injection, the empirical result for very thin oxides may be gate leakage currents and/or catastrophic device failure.
Another difficulty associated with very thin conventional gate oxides is polysilicon depletion. In p-channel transistors, the source and drain are commonly formed in the substrate by implanting a p-type dopant, such as boron. The implant also deposits boron into the polysilicon of the gate electrode. Subsequent thermal processing steps to fabricate a conventional p-channel field effect transistor frequently cause boron to diffuse from the gate electrode through the gate oxide layer and into the channel region. If the amount of boron diffused is sufficiently high, the electrical performance of the field effect transistor may be severely degraded due to polysilicon depletion. The potential for boron diffusion increases with decreasing oxide thickness.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.